1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, and more particularly to an electrode pad structure for reducing noises transmitted between an electrode pad and an element and a manufacture method thereof.
2. Description of the Prior Arts
Recently, in a large scale integrated circuit (LSI) in which analog and digital circuits co-exist, an adverse effect of a substrate noise on an analog circuit property has been increased. Since the digital circuit is operated at a high speed, the substrate noise generated during the circuit operation becomes larger relative to a signal voltage. Therefore, it is important to prevent a noise interference between the analog and digital circuits which are formed on the same semiconductor substrate. Especially, when a noise enters the substrate from a digital signal input/output electrode pad (hereinafter referred to as the signal-input/output pad) with a larger area as compared with the element, a substrate potential under the analog circuit is made unstable by the noise. This adversely affects the analog circuit property. To solve the problem, i.e., not to give to an analog circuit substrate the adverse effect of the substrate noise generated in the signal input/output pad, a structure shown in FIG. 1A is proposed.
This prior art uses a technique which is disclosed in the Japanese Patent Application Laid-open No. Sho 59-43536. On a P-type semiconductor substrate 1 formed are a P.sup.+ -type embedded layer 2 and an epitaxially grown P-type region 3. An element region is defined by a field oxide film 4. In the element region formed are a gate oxide film 5, a gate electrode 6, an LDD diffused layer 7, a side wall 8 and a source/drain region 9 with a high concentration of impurities. These constitute an MOS transistor 100 on which an interlayer insulating film 10 is formed. Also, source and drain electrodes 12 and 13 are formed via contact holes 11. The MOS transistor 100 (shown by a dotted circle) is enlarged and shown in FIG. 1C. Inside the interlayer insulating film 10 on the field oxide film 4, a noise shielding conductive film 17 is formed of, for example, an aluminum film or the like. In an upper region formed is a signal input/output pad 14. Also, the noise shielding conductive film 17 is electrically connected via a contact hole 11a to a GND pad 18. In the constitution, as shown in FIG. 1B, by applying a GND voltage to the conductive film 17 which is provided right under the signal input/output pad 14, noises made by digital signals transmitted to the signal input/output pad 14 are shielded by the conductive film 17. Thereby, the noises are prevented from being propagated to the semiconductor substrate 1 and the elements which are provided under the conductive film 17 as shown by a chain line A.
Alternatively, as disclosed in the Japanese Patent Application Laid-open No. Sho 59-43536 and shown in FIG. 2, a noise shielding conductive film 20 is formed right under a signal wiring 19 which is connected to a signal input/output pad (not shown). Also, right above the film 20 formed is a GND electrode 21. The noise shielding conductive film 20 and the GND electrode 21 are connected via a through hole 11b. Thereby, the signal wiring 19 is surrounded by the conductive films 20 and 21 which have GND potentials. The technique is proposed for shielding noises. The same MOS transistor 100 as shown in FIG. 1C is used. Numeral 22 denotes an insulating film. The similar technique is also described in the Japanese Patent Application Laid-open No. Hei 2-82531.
In the conventional structure, however, noise shielding conductive films need to be independently formed right under and above the signal input/output pad. Therefore, the number of manufacture processes of the semiconductor device is disadvantageously increased. Also, a distance between the signal input/output pad and the noise shielding conductive film is short. Especially, since the conductive film formed right under the signal input/output pad is formed in the interlayer insulating film, the distance is shortened. Also, parasitic capacities of the signal input/output pad and the associated signal conductor are increased. Input/output signals are disadvantageously delayed largely.